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general description the max1366/max1368 low-power, 4.5- and 3.5-digit, panel meters feature an integrated sigma-delta analog- to-digital converter (adc), led display drivers, voltage digital-to-analog converter (dac), and a 4?0ma (or 0 to 16ma) current driver. the max1366/max1368? analog input voltage range is programmable to either ?v or ?00mv. the max1368 drives a 3.5-digit (1999 count) display and the max1366 drives a 4.5-digit (?9,999 count) display. the adc output directly drives the led display as well as the voltage dac, which, in turn, drives the 4?0ma (or 0 to 16ma) current-loop output. in normal operation, the 0 to 16ma/4?0ma current- loop output follows the ?v or ?00mv analog input to drive remote panel-meter displays, data loggers, and other industrial controllers. for added flexibility, the max1366/max1368 allow direct access to the adc result, dac output, and the v/i converter input. the sigma-delta adc does not require external preci- sion integrating capacitors, autozero capacitors, crystal oscillators, charge pumps, or other circuitry commonly required in dual-slope adc panel-meter circuits. on- chip analog input and reference buffers allow direct interface with high-impedance signal sources. excellent common-mode rejection and digital filtering provides greater than 100db rejection of simultaneous 50hz and 60hz line noise. other features include data hold and peak detection and overrange/underrange detection. the max1366/max1368 require a 2.7v to 5.25v supply, a 4.75v to 5.25v v/i supply, and a 7v to 30v loop sup- ply. they are available in a space-saving (7mm x 7mm), 48-pin tqfp package and operate over the extended (-40? to +85?) temperature range. applications industrial process control automated test equipment data-acquisition systems digital panel meters digital voltmeters digital multimeters features ? microcontroller (?)-interface, digital panel meter 20-bit sigma-delta adc 4.5-digit resolution (?9,999 count, max1366) 3.5-digit resolution (?999 count, max1368) no integrating/autozeroing capacitors 100m ? input impedance ?00mv or ?.000v input range ? led display common-cathode 7-segment led driver programmable led current (0 to 20ma) 2.5hz update rate ? output dac and current driver ?5-bit dac with 14-bit linear v/i converter selectable 0 to 16ma or 4?0ma current output unipolar/bipolar modes ?0? zero scale, ?0ppmfs/? (typ) ?.5% gain error, ?5ppmfs/? (typ) separate 7v to 30v supply for current-loop output ? 2.7v to 5.25v adc/dac supply ? 4.75v to 5.25v v/i converter supply ? internal 2.048v reference or external reference ? spi-/qspi-/microwire-compatible serial interface ? 48-pin, 7mm x 7mm tqfp package max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ________________________________________________________________ maxim integrated products 1 selector guide 19-3977; rev 0; 1/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max1366 ecm -40? to +85? 48 tqfp max1368 ecm -40? to +85? 48 tqfp ordering information part package code resolution (digits) max1366ecm c48-6 4.5 max1368ecm c48-6 3.5 pin configuration appears at end of data sheet. typical operating circuits appear at end of data sheet. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = dac_vdd = +2.7v to +5.25v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, v reg_amp = +5.0v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (with reference to gnd, unless otherwise specified.) av dd ,dv dd .................................................................... -0.3v to +6.0v ain+, ain-, ref+, ref-.........................v negv to (av dd + 0.3v) reg_force, cmp, dac_vdd, dacvout, conv_in, 4-20out .............................-0.3v to (av dd + 0.3v) en_bpm, en_i, refsele, dacdata_sel, clk, eoc , cs_dac , sclk, din dout .....................................................-0.3v to (dv dd + 0.3v) negv .......................................................-2.6v to (av dd + 0.3v) led_en....................................................-0.3v to (dv dd + 0.3v) set...........................................................-0.3v to (av dd + 0.3v) reg_amp, reg_vdd ...........................................-0.3v to +6.0v ledg .....................................................................-0.3v to +0.3v gnd_dac .............................................................-0.3v to +0.3v gnd_v/i.................................................................-0.3v to +0.3v seg_ to ledg.........................................-0.3v to (v ledv + 0.3v) dig_ to ledg..........................................-0.3v to (v ledv + 0.3v) lowbatt ................................................-0.3v to (av dd + 0.3v) ref_dac .................................................-0.3v to (av dd + 0.3v) dacvout ................................................-0.3v to (av dd + 0.3v) dig_ sink current .............................................................300ma dig_ source current...........................................................50ma seg_ sink current ..............................................................50ma seg_ source current..........................................................50ma maximum current input into any other pin ........................50ma continuous power dissipation (t a = +70?) 48-pin tqfp (derate 22.7mw/? above +70?).....1818.2mw operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units adc accuracy max1366 -19,999 +19,999 noise-free resolution max1368 -1999 +1999 counts 2.000v range ? integral nonlinearity (note 1) inl 200mv range ? counts range-change ratio (v ain+ - v ain- = 0.100v) on 200mv range; (v ain+ - v ain- = 0.100v) on 2.0v range 10:1 ratio rollover error v ain+ - v ain- = full scale ? counts output noise 10 ? p-p offset error (zero input reading) v ain+ - v ain- = 0 (note 2) -0 +0 counts gain error (note 3) -0.5 +0.5 %fsr offset drift (zero reading drift) v ain+ - v ain- = 0 (note 4) 0.1 ?/? gain drift ? ppm/? input conversion rate external clock frequency 4.9152 mhz external clock duty cycle 40 60 % internal clock 5 update rate external clock, f clk = 4.9152mhz 5 hz analog inputs (ain+, ain-) (bypass to gnd with 0.1? or greater capacitors) range bit = 0 -2.0 +2.0 ain input voltage range (note 5) range bit = 1 -0.2 +0.2 v
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units ain absolute input voltage range to gnd -2.2 +2.2 v internal clock mode, 50hz and 60hz ?% 100 normal-mode 50hz and 60hz rejection (simultaneously) external clock mode, 50hz and 60hz ?%, f clk = 4.9152mhz 100 db common-mode 50hz and 60hz rejection (simultaneously) cmr for 50hz and 60hz ?%, r source < 10k ? 150 db common-mode rejection cmr at dc 100 db input leakage current 10 na input capacitance 10 pf average dynamic input current (note 6) -20 +20 na low-battery voltage monitor (lowbatt) lowbatt trip threshold 2.048 v lowbatt leakage current 10 pa hysteresis 20 mv internal reference (ref- = gnd, intref = dv dd ) ref input voltage v ref av dd = 5v 2.007 2.048 2.089 v ref output short-circuit current 1ma ref output temperature coefficient tc vref 40 ppm/? load regulation i source = 0 to 300?, i sink = 0 to 30? 6 ?/? line regulation 50 ?/v 0.1hz to 10hz 25 noise voltage 10hz to 10khz 400 ? p-p external reference (intref bit = 0) ref input voltage differential, (v ref+ - v ref- ) 2.048 v absolute ref+, ref- input voltage to gnd (v ref+ must be greater than v ref- ) -2.2 +2.2 v internal clock mode, 50hz and 60hz ?% 100 normal-mode 50hz and 60hz rejection (simultaneously) external clock mode, 50hz and 60hz ?%, f clk = 4.9152mhz 120 db common-mode 50hz and 60hz rejection (simultaneously) cmr for 50hz and 60hz ?%, r source < 10k ? 150 db common-mode rejection cmr at dc 100 db input leakage current 10 na electrical characteristics (continued) (av dd = dv dd = dac_vdd = +2.7v to +5.25v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, v reg_amp = +5.0v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25?, unless otherwise noted.)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = dac_vdd = +2.7v to +5.25v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, v reg_amp = +5.0v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units input capacitance 10 pf average dynamic input current (note 6) -20 +20 na charge pump output voltage negv c negv = 0.1? to gnd -2.60 -2.42 -2.30 v digital inputs (sclk, din, cs , clk) input current i in v in = 0 or dv dd -10 +10 ? input low voltage v inl 0.3 x dv dd v input high voltage v inh 0.7 x dv dd v input hysteresis v hys dv dd = 3v 200 mv digital outputs (dout, eoc ) output low voltage v ol i sink = 1ma 0.4 v output high voltage v oh i source = 200? 0.8 x d vdd v tri-state leakage current i l -10 +10 ? tri-state output capacitance c out 15 pf adc power supply (note 10) av dd voltage av dd 2.70 5.25 v dv dd voltage dv dd 2.70 5.25 v power-supply rejection av dd psr a (note 7) 80 db power-supply rejection dv dd psr d (note 7) 100 db 640 av dd current (notes 8, 9) i avdd standby mode 305 ? dv dd = +5.25v 320 dv dd = +3.3v 180 dv dd current (notes 8, 9) i dvdd standby mode 20 ? dac power supply dac supply voltage v dac_vdd 2.70 5.25 v dac supply current 0.10 0.21 ma linear regulator and v/i converter power requirements reg_amp supply voltage v reg_amp 4.75 5.25 v reg_amp supply current 0.19 0.30 ma reg_vdd voltage v reg_vdd 5.20 v
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = dac_vdd = +2.7v to +5.25v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, v reg_amp = +5.0v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units reg_vdd supply current includes 20ma programmed current 25.2 27.4 ma led drivers (table 7) led supply voltage v ledv 2.70 5.25 v led shutdown supply current i shdn 10 ? led supply current i ledv seven segments and decimal point on, r set = 25k ? 176 180 ma max1366 512 display scan rate f osc max1368 640 hz segment current slew rate i seg / ? t25 ma/? dig_ voltage low v dig i dig_ = 176ma 0.178 0.300 v segment-drive source-current matching ? i seg 3 ?0 % segment-drive source current i seg v ledv - v seg = 0.6v, r set = 25k ? 4-20out output accuracy zero-scale error 4ma or 0ma, at +25? ?0 ?0 ? zero-scale error tempco 40 p p mfs / c gain error 4ma or 0ma, at +25? ?.2 ?.5 %fs gain-error tempco 25 p p mfs / c span linearity 2 4a power-supply rejection psr v ext = 7v to 36v 4 ?/v signal path noise 10pf to agnd on 4-20out 2.0 ? rms 4?0ma current limit limited to 12.5 x v ref / 1.28k ? 20 ma timing characteristics (notes 11, 12, figure 8) sclk operating frequency f sclk dv dd = 2.7v 0 4.2 mhz sclk pulse-width high t ch 100 ns sclk pulse-width low t cl 100 ns din-to-sclk setup t ds 50 ns din-to-sclk hold t dh 0ns cs fall to sclk rise setup t css 50 ns sclk rise to cs rise hold t csh 0ns sclk fall to dout valid t do c load = 50pf, figures 11, 12 120 ns
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 6 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = dac_vdd = +2.7v to +5.25v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, v reg_amp = +5.0v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?. internal clock mode, unless otherwise noted. all specifications are at t a = t min to t max . typical values are at t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units cs rise to dout disable t tr c load = 50pf, figures 11, 12 120 ns cs fall to dout enable t dv c load = 50pf, figures 11, 12 120 ns note 1: integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and offset error. note 2: offset calibrated. see offset_cal1 and offset_cal2 in the on-chips registers section. note 3: offset nulled. note 4: offset-drift error is eliminated by recalibration at the new temperature. note 5: the input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pa ir. note 6: v ain+ or v ain- = -2.2v to +2.2v. v ref+ or v ref- = -2.2v to +2.2v. all input structures are identical. production tested on ain+ and ref+ only. v ref+ must always be greater than v ref- . note 7: measured at dc by changing the power-supply voltage from 2.7v to 5.25v and measuring the effect on the conversion error with external reference. psrr at 50hz and 60hz exceeds 120db with filter notches at 50hz and 60hz ( figure 1). note 8: clk and sclk are disabled. note 9: led drivers are disabled. note 10: power-supply currents are measured with all digital inputs at either gnd or dv dd and with the device in internal clock mode. note 11: all input signals are specified with t rise = t fall = 5ns (10% to 90% of dv dd ) and are timed from a voltage level of 50% of dv dd , unless otherwise noted. note 12: see the serial-interface timing diagrams (figures 7?1). 0 300 200 100 400 500 600 700 800 900 1000 2.7 3.7 3.2 4.2 4.7 5.2 supply current vs. supply voltage max1366/68 toc01 supply voltage (v) supply current ( a) dac_vdd av dd dv dd 0 200 100 400 300 600 500 700 -40 10 -15 35 60 85 supply current vs. temperature max1366/68 toc02 temperature ( c) supply current ( a) av dd dv dd dac_vdd max1366 offset error vs. supply voltage max1366/68 toc03 supply voltage (v) offset error (lsb) 4.75 4.25 3.75 3.25 -0.11 -0.06 -0.01 0.04 0.09 0.14 0.19 -0.16 2.75 5.25 t ypical operating characteristics (a vdd = d vdd = +5v, v dac_vdd = +5.0v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?, range bit = 1, internal clock mode. t a = +25?, unless otherwise noted.)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output _______________________________________________________________________________________ 7 t ypical operating characteristics (a vdd = d vdd = +5v, v dac_vdd = +5.0v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?, range bit = 1, internal clock mode. t a = +25?, unless otherwise noted.) max1366 offset error vs. temperature max1366/68 toc04 temperature ( c) offset error (lsb) 60 50 10 20 30 40 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 -0.2 070 max1366 gain error vs. supply voltage max1366/68 toc05 supply voltage (v) gain error (% full scale) 4.75 4.25 3.25 3.75 -0.08 -0.04 -0.06 -0.02 0 0.02 0.04 0.06 0.08 -0.10 2.75 5.25 max1366 gain error vs. temperature max1366/68 toc06 temperature ( c) gain error (% full scale) 60 50 30 40 20 10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 -0.10 070 max1366 ( 200mv input range) inl vs. output code max1366/68 toc07 output code inl (counts) 10,000 0 -10,000 -0.5 0 0.5 1.0 -1.0 -20,000 20,000 max1366 ( 2v input range) inl vs. output code max1366/68 toc08 output code inl (counts) 10,000 0 -10,000 -0.5 0 0.5 1.0 -1.0 -20,000 20,000 noise distribution max1366/68 toc09 noise (lsb) percentage of units (%) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 5 10 15 20 25 0 -0.2 internal reference voltage vs. temperature max1366/68 toc10 temperature ( c) reference voltage (v) 60 50 40 30 20 10 2.046 2.045 2.047 2.049 2.048 2.051 2.050 2.053 2.052 2.054 2.044 070 internal reference voltage vs. analog supply voltage max1366/68 toc11 supply voltage (v) reference voltage (v) 4.75 4.25 3.75 3.25 2.045 2.046 2.047 2.048 2.049 2.050 2.044 2.75 5.25 data output rate vs. temperature max1366/68 toc12 temperature ( c) data output rate (hz) 60 35 -15 10 4.92 4.98 4.96 4.94 5.00 5.02 5.04 5.06 5.08 5.10 4.90 -40 85
data output rate vs. supply voltage max1366/68 toc13 supply voltage (v) data output rate (hz) 4.74 4.23 3.21 3.72 4.995 4.990 4.985 5.000 5.005 5.010 5.015 5.020 4.980 2.70 5.25 offset error vs. common-mode voltage max1366/68 toc14 common-mode voltage (v) offset error (lsb) 1.5 1.0 -1.5 -1.0 -0.5 0 0.5 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 -2.0 2.0 v neg startup scope shot max1366/68 toc15 20ms/div 2v/div 1v/div v dd v neg charge-pump output voltage vs. analog supply voltage max1366/68 toc16 supply voltage (v) v neg voltage (v) 4.75 4.25 3.75 3.25 -2.48 -2.46 -2.44 -2.42 -2.40 -2.50 2.75 5.25 segment current vs. supply voltage max1366/68 toc17 supply voltage (v) segment current ( a) 4.74 4.23 3.72 3.21 5 10 15 20 25 30 0 2.70 5.25 r iset = 25k ? -0.2 0 -0.1 0.2 0.1 0.3 0.4 -40 10 -15 35 60 85 dac zero-code offset error vs. temperature max1366/68 toc18 temperature ( c) offset error (lsb) max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 8 _______________________________________________________________________________________ t ypical operating characteristics (a vdd = d vdd = +5v, v dac_vdd = +5.0v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?, range bit = 1, internal clock mode. t a = +25?, unless otherwise noted.)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output _______________________________________________________________________________________ 9 t ypical operating characteristics (continued) (a vdd = d vdd = +5v, v dac_vdd = +5.0v, gnd = 0, ledg = 0, v ledv = +2.7v to +5.25v, v ref+ - v ref- = 2.048v (external reference), v ext = 7v, c ref+ = 0.1?, ref- = gnd, c negv = 0.1?, range bit = 1, internal clock mode. t a = +25?, unless otherwise noted.) -0.30 -0.20 -0.25 -0.10 -0.15 -0.05 0 -40 10 -15 35 60 85 dac gain error vs. temperature max1366/68 toc19 temperature ( c) gain error (lsb) 4-20out = 21.7ma conv_in = 1v 10ma/div 500mv/div step response max1366/68 toc20 100 s/div -50 -20 -30 -40 0 -10 40 30 20 10 50 -40 -20 0 20 40 60 80 4-20out zero-scale error vs. temperature max1366/68 toc21 temperature ( c) current output ( a) external reference = 2.048v -50 -20 -30 -40 0 -10 40 30 20 10 50 -40 -20 0 20 40 60 80 4-20out gain error vs. temperature max1366/68 toc22 temperature ( c) gain error (%) external reference = 2.048v 4?0ma mode 0 to 16ma mode -150 -100 -50 0 50 100 150 48 610121 4161820 power-supply rejection vs. current output (4-20out) max1366/68 toc23 4-20out output current (ma) power-supply rejection (na/v) -0.5 0 0.5 1.0 1.5 2.0 2.5 -20,000 -10,000 0 10,000 20,000 4-20out vs. dac code (4-20out span linearity) max1366/68 toc24 dac code (counts) span linearity ( a) offset enabled (en_i = high)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 10 ______________________________________________________________________________________ pin name function 1 ain+ positive analog input. positive side of fully differential analog input. bypass ain+ to gnd with a 0.1? or greater capacitor. 2 ain- negative analog input. negative side of fully differential analog input. bypass ain- to gnd with a 0.1? or greater capacitor. 3 gnd ground. connect to star ground. 4av dd analog positive supply voltage. connect av dd to a +2.7v to +5.25v power supply. bypass av dd to gnd with a 0.1? capacitor. 5dv dd digital positive supply voltage. connect dv dd to a +2.7v to +5.25v power supply. bypass dv dd to gnd with a 0.1? capacitor. 6 set segment current set. connect to ground through a resistor to set the segment current. see table 7 for segment-current selection. 7 reg_vdd v/i converter regulated supply output. reg_ vdd is typically 2.5v. 8 reg_force reg_vdd control. drives the gate of external depletion mode fet. 9 reg_amp regulator/reference buffer supply. connect to a 4.75v to 5.25v power supply. 10 cmp regulator compensation node. connect a 0.1? capacitor from cmp to reg_force. 11 dac_vdd dac analog supply. connect dac_vdd to a +2.7v to +5.25v power supply. 12 dacvout dac voltage output. dac output impedance is typically 6.2k ? . 13 conv_in v/i converter input 14 4?0out 4?0ma (0 to 16ma) current-loop output. referenced to gnd. 15 gnd_dac dac analog ground. connect to star ground. 16 gnd_v/i v/i converter analog ground. connect to star ground. 17 ref_dac v-to-i converter/dac reference input. connect a voltage source for external reference operation or leave floating for internal reference. bypass ref_dac with a 0.1? capacitor to gnd for either internal or external reference operation. 18 en_bpm acti ve- h i g h v /i- c onver ter bi p ol ar - m od e e nab l e. s et hi g h for b i p ol ar m od e. s et l ow for uni p ol ar m od e. 19 en_i acti ve- h i g h v /i- c onver ter 4m a o ffset e nab l e. s et l ow for 0 to 16m a outp ut. s et hi g h for 420m a 20 refsele dac external reference selection. set low for internal reference. set high for external reference. leave ref_dac unconnected when refsele is low. 21 dacdata_sel dac data-source select. set high to select dac register. set low to have the dac follow the adc output. 22 cs_dac dac spi chip select. see table 8. 23 clk external clock input. when the extclk register bit is set to one, clk is the master clock input for the modulator, filter, and dac. when the extclk register bit is reset to zero, the internal clock is used. the default power-on state is extclk = 0 (internal clock mode). connect clk to gnd or dv dd when using internal clock. 24 eoc active-low end-of-conversion logic output. a logic-low at eoc indicates that a new adc result is available in the adc result register. pin description
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 11 pin name function 25 sclk serial clock input. apply an external clock to sclk to facilitate communication through the serial bus. sclk may idle high or low. 26 dout serial data output. dout presents serial data in response to register queries. data shifts out on the falling edge of sclk. dout goes high impedance when cs is high. 27 din serial data input. data present at din is shifted into the internal registers in response to a rising edge at sclk when cs is low. 28 cs active-low chip-select input. forcing cs low activates the serial interface. (see table 8.) 29 ledg led segment-drivers ground 30 dig0 digit 0 driver out (connected to gled for the max1368) 31 dig1 digit 1 driver out 32 dig2 digit 2 driver out 33 dig3 digit 3 driver out 34 dig4 digit 4 driver out 35 sega segment a driver 36 segb segment b driver 37 ledv led-display segment-driver supply. connect to a +2.7v to +5.25v supply. bypass with a 0.1? capacitor to ledg. 38 segc segment c driver 39 segd segment d driver 40 sege segment e driver 41 segf segment f driver 42 segg segment g driver 43 segdp segment decimal-point driver 44 led_en active-high led enable. the max1366/max1368 display driver turns off when led_en is low. the max1366/max1368 led-display driver turns on when led_en is high. 45 negv -2.5v charge-pump voltage output. connect a 0.1? capacitor to gnd. 46 lowbatt low-battery-voltage monitor. when the lowbatt input voltage is lower than 2.048v, the lowbatt bit in the status register is set to one. 47 ref- negative reference voltage input. for internal reference operation, connect ref- to gnd. for external reference operation, bypass ref- to gnd with a 0.1? capacitor and set v ref- from -2.2v to +2.2v (v ref+ > v ref- ). 48 ref+ positive reference voltage input. for internal reference operation, connect a 4.7? capacitor from ref+ to gnd. for external reference operation, bypass ref+ to gnd with a 0.1? capacitor and set v ref+ from -2.2v to +2.2v, provided that v ref+ > v ref- . pin description (continued)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 12 ______________________________________________________________________________________ detailed description the max1366/max1368 low-power, highly integrated adcs with led drivers convert a ?v differential input voltage (one count is equal to 100? for the max1366 and 1mv for the max1368) with a sigma-delta adc and output the result to an led display. an additional ?00mv input range (one count is equal to 10? for the max1366 and 100? for the max1368) is available to measure small signals with finer resolution. in addition to displaying the results on an led display, these devices feature a dac and v-to-i converter for 4?0ma (or 0 to 16ma) current output that proportional- ly follows the adc input. the max1366/max1368 use an external depletion-mode nmos transistor to regulate 7v to 30v for the v/i converter. use the 4?0ma (or 0 to 16ma) output to drive a remote display, data logger, plc input, or other 4?0ma devices in a current loop. the max1366/max1368 interface with a ? using an spi-/qspi-/microwire-compatible serial interface. for added flexibility, the max1366/max1368 allow direct access to the adc register, led display register, and dac output register using the spi interface. the max1366/max1368 include a 2.048v reference, internal charge pump, and a high-accuracy on-chip oscillator. the devices feature on-chip buffers for the dif- ferential input signal and external-reference inputs, allowing direct interface with high-impedance signal sources. in addition, they use continuous internal offset calibration and offer > 100db of 50hz and 60hz line- noise rejection. other features include data hold and peak detection and overrange/underrange detection. analog input protection the max1366/max1368 provide internal protection diodes that limit the analog input range on ain+, ain-, ref+, and ref- from negv to (av dd + 0.3v). if the analog input exceeds this range, limit the input current to 10ma. led driver ledg sega segg dig0(1) dig4(4) led_en adc input buffer -2.5v ain+ ain- ref+ ref- negv +2.5v 2.048v bandgap reference serial i/o and control gnd charge pump -2.5v output dac dac ref buffer av dd dv dd clk sclk din dout cs cs_dac eoc dacdata_sel 5v regulator v/i converter current summer and amplifier offset generator en_bpm en_i dacvout 4-20out reg_force set refsele reg_amp ref_dac conv_in cmp reg_vdd dac_vdd ledv display register adc register cs_dac dac register max1366 (max1368) din sclk functional diagram
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 13 internal analog input/reference buffers the max1366/max1368 analog input/reference buffers allow the use of high-impedance signal sources. the input buffers?common-mode input range allows the ana- log inputs and the reference to range from -2.2v to +2.2v. modulator the max1366/max1368 perform analog-to-digital con- versions using a single-bit, 3rd-order, sigma-delta mod- ulator. the sigma-delta modulator converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. the modulator quantizes the input signal at a much higher sample rate than the bandwidth of the input. the max1366/max1368 modulator provides 3rd-order fre- quency shaping of the quantization noise resulting from the single-bit quantizer. the modulator is fully differen- tial for maximum signal-to-noise ratio and minimum sus- ceptibility to power-supply noise. a single-bit data stream is then presented to the digital filter to remove the frequency-shaped quantization noise. digital filtering the max1366/max1368 contain an on-chip digital low- pass filter that processes the data stream from the modulator using a sinc 4 response: the sinc 4 filter has a settling time of four output data periods (4 x 200ms). the max1366/max1368 have 25% overrange capability built into the modulator and digital filter. the digital filter is optimized for the f clk equal to 4.9152mhz. the frequency response of the sinc 4 filter is calculated as follows: where n is the oversampling ratio, and f m = n x output data rate = 5hz. filter characteristics figure 1 shows the filter frequency response. the sinc 4 characteristic -3db cutoff frequency is 0.228 times the first notch frequency (5hz). the oversampling ratio (osr) for the max1368 is 128 and the osr for the max1366 is 1024. the output data rate for the digital fil- ter corresponds to the positioning of the first notch of the filter? frequency response. the notches of the sinc 4 filter are repeated at multiples of the first notch frequency. the sinc 4 filter provides an attenuation of better than 100db at these notches. for example, 50hz is equal to 10 times the first notch frequency and 60hz is equal to 12 times the first notch frequency. for large step changes at the input, allow a settling time of 800ms before valid data is read. clock modes configure the max1366/max1368 to use either the internal oscillator or an externally applied clock to drive the modulator, filter, and dac. set the extclk bit in the control register to zero to put the device in internal clock mode. set the extclk bit to one to put the device in external clock mode. when using the internal oscillator, connect clk to gnd or dv dd . the max1366/max1368 operate with a 4.9152mhz clock to achieve maximum rejection of 50hz/60hz common- mode, power-supply, and normal-mode noise. internal clock mode the max1366/max1368 contain an internal oscillator. the power-up condition for the max1366/max1368 is internal clock operation with the extclk bit in the con- trol register equal to zero. using the internal oscillator saves board space by removing the need for an exter- nal clock source. external-clock mode for external clock operation, set the extclk bit in the control register to one and drive clk with a 4.9152mhz hz z n hf n n f f f f n z m m () () () sin sin () = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 11 1 1 4 4 1 sin( ) x x ? ? ? ? ? ? 4 frequency (hz) gain (db) 50 40 30 20 10 -160 -120 -80 -40 0 -200 060 figure 1. frequency response of the sinc 4 filter (notch at 60hz)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 14 ______________________________________________________________________________________ clock source for best 50hz/60hz rejection perfor- mance. other external clock frequencies allow for cus- tom conversion rates. a 2.4576mhz clock signal reduces the conversion rate and the led update rate by a factor of two while keeping good 50hz/60hz noise rejection. the max1366/max1368 operate with an external clock source of up to 5.05mhz. charge pump the max1366/max1368 contain an internal charge pump to provide the negative supply voltage for the internal analog input/reference buffers. the bipolar input range of the analog input/reference buffers allows this device to accept negative inputs with high source impedances. connect a 0.1? capacitor from negv to gnd. led driver (table 1) the max1366 has a 4.5-digit common-cathode display driver, and the max1368 has a 3.5-digit common-cath- ode display driver. figures 2 and 3 show the connection schemes for a standard seven-segment led display. the led update rate is 2.5hz. the max1366/max1368 automatically display the results of the adc, if desired. the max1366/max1368 also allow independent control of the led driver through the serial interface, allowing for data processing of the adc result before showing the result on the led. additionally, each led segment can be individually controlled (see the led segment-display register sections). figure 4 shows a typical common-cathode configura- tion for two digits. in common-cathode configuration, the cathodes of all leds in a digit are connected together. each segment driver of the max1366/ max1368 connects to its corresponding led? anodes. for example, segment driver sega connects to all led segments designated as a. similar configurations are used for other segment drivers. the max1366/max1368 use a multiplexing scheme to drive one digit at a time. the scan rate is fast enough to make the digits appear to be lit. figure 5 shows the data-timing diagram for the max1366/max1368 where t is the display scan period (typically around 1/512hz or 1.9531ms). t on in figure 5 denotes the amount of time each digit is on and is calculated as follows: decimal-point control the max1366/max1368 allow for full decimal-point control and feature leading-zero suppression. use the dpon, dpset1, and dpset2 bits in the con- trol register to set the value of the decimal point ( tables 2 and 3 ). the max1366/max1368 overrange and underrange display is shown in table 4 . current output the max1366/max1368 feature a 4?0ma (0 to 16ma) current output for driving remote panel meters, data log- gers, and process controllers in industrial applications. the dac output is proportional to the input of the adc and led display. in the simplest configuration, connect dac_vout directly to conv_in to have the current out- put (4?0ma or 0 to 16ma) follow the analog inputs. t tms s on == = 5 1 95312 5 390 60 . . a b c a aaa d digit 4 digit 3 digit 2 digit 1 digit 0 d ddd e g f eee gggg f fff bbbb cc cc dp dp dp dp dp figure 2. segment connection for the max1366 (4.5 digits) a b aa a d digit 4 digit 3 digit 2 digit 1 ddd e g f ee ggg fff bbb cc c dp dp dp dp c figure 3. segment connection for the max1368 (3.5 digits) seg_sel spi/ adc hold peak display values form 1xxx led segment registers 01xx led display register (user written) 001x led display register 00 01 peak register 00 00 adc result register table 1. led priority table x = don? care.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 15 a a a digit 1 digit 2 segdp segg segf sege segd segc segb sega dd ee gg ff bb cc dp dp b c d e f g dp a b c d e f g dp figure 4. 2-digit common-cathode configuration 1 43210432 04 t t on digit 4 (msd) interdigit blanking time digit 2 digit 1 digit 0 (lsd) data msd lsd figure 5. led voltage waveform dpon dpset1 dpset2 display output zero input reading 10 0 1888 0. 10 1 188.8 0.0 11 0 18.88 0.00 11 1 1.888 0.000 table 3. decimal-point control table max1368 dpon dpset1 dpset2 display output zero input reading 00 0 18888 0 00 1 18888 0 01 0 18888 0 01 1 18888 0 10 0 1888.8 0.0 10 1 188.88 0.00 11 0 18.888 0.000 11 1 1.8888 0.0000 table 2. decimal-point control table max1366
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 16 ______________________________________________________________________________________ custom signal conditioning can be inserted between dac_vout and conv_in, or conv_in can be driven independently by a voltage source if desired. see figures 20?3 for the transfer functions of the dac and v/i converter. current offset set en_i high for a current span of 4?0ma. set en_i low for a current span of 0 to 16ma. see table 5 for current output. unipolar mode set en_bpm low to engage unipolar operation. in unipo- lar mode, the current output at 4-20out (4?0ma or 0 to 16ma) maps the analog input voltage (0 to 2v or 0 to 200mv). negative voltages at the analog input result in a 4ma or 0ma output, depending on the en_i setting. see table 5 for current output. see figures 21 and 22. bipolar mode set en_bpm high to engage bipolar operation. in bipo- lar mode, the current output at 4-20out (4?0ma or 0 to 16ma) maps the analog input voltage (2v or ?00mv). in bipolar mode, a 0v analog input maps to midscale (12ma). see table 5 for current output. also see figures 21 and 22 . cs or cs_dac sclk din dout t csh t cl t ds t dh t dv t ch t do t tr t csh t css figure 6. adc and dac timing diagram sclk cs din dout 10 rs4 rs3 rs2 rs1 d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 rs0 x d15 d14 d13 d12 d11 d10 control byte data byte figure 7. serial-interface, 16-bit, write timing diagram condition max1368 max1366 overrange 1--- 1---- underrange -1--- -1---- table 4. led during overrange and underrange conditions note: the max1366/max1368 expect a 6k ? (typ) source impedance from the voltage source driving conv_in.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 17 cs cs_dac sclk din dout 10 rs4 rs3 rs2 rs1 d7 d6 d5 d4 d3 d2 d1 d0 rs0 x control byte data byte figure 8. serial-interface, 8-bit, write timing diagram sclk cs din dout 11 rs4 rs3 rs2 rs1 rs0 x d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 d15 d14 d13 d12 d11 d10 control byte data byte cs_dac figure 9. serial-interface, 16-bit, read timing diagram current output (ma) analog input unipolar mode (en_i = low) unipolar mode (en_i = high) bipolar mode (en_i = low) bipolar mode (en_i = high) negative full scale 0 4 0 4 0v 0 4 8 12 positive full scale 16 20 16 20 table 5. current-output table
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 18 ______________________________________________________________________________________ sclk cs_dac din d7 d6 d5 d4 d3 d2 d1 d0 d8 d9 d15 d14 d13 d12 d11 d10 data byte cs figure 11. dac serial interface dout 6k ? gnd c load 50pf dout 6k ? c load 50pf gnd dv dd a) v oh to high impedance b) v ol to high impedance figure 12. load circuits for disable time dout 6k ? gnd c load 50pf dout 6k ? c load 50pf gnd dv dd b) high impedance to v oh and v ol to v oh b) high impedance to v ol and v oh to v ol figure 13. load circuits for enable time sclk cs din dout 11 rs4 rs3 rs2 rs1 rs0 x d7 d6 d5 d4 d3 d2 d1 d0 control byte data byte cs_dac figure 10. serial-interface, 8-bit, read timing diagram
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 19 max1366 max1368 av dd dv dd 10 f 10 f 0.1 f 0.1 f 0.1 f 0.1 f analog supply ferrite bead r ref r r active gauge dummy gauge ref+ ref- ain+ ain- 4-20out 4?0ma/0 to 16ma current-loop output gnd 0.1 f 0.1 f sclk din cs eoc dout figure 14. strain-gauge application with the max1366/max1368 max1366 max1368 max6062 +5v +2.048v temp sensor thermocouple junction 0.1 f 0.47 f spi c ain+ ain- ref+ ref- gnd 4-20out negv 4?0ma/0 to 16ma current-loop output figure 15. thermocouple application with the max1366/max1368
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 20 ______________________________________________________________________________________ 5.2v linear regulator with compensation the max1366/max1368 feature a 5.2v linear regulator. the 5.2v regulator consists of an op amp and connec- tions to an external depletion-mode fet. the 5.2v reg- ulator regulates the loop voltage that powers the voltage-to-current converter and the rest of the trans- mitter circuitry. the regulator output voltage is available at reg_vdd and is given by the equation: v reg_vdd = 2.54 x v ref+ the fet breakdown and saturation voltages determine the usable range of loop voltages (v ext ). the external fet parameters such as v gs (off), i dss , and transcon- ductance must be chosen so that the op amp output on the reg_force pin can control the fet operating point while swinging in the range from vreg_amp to reg_vdd. see the selecting depletion mode fet section in the applications information section. connect a 0.1? capacitor between cmp and reg_force to ensure stable operation of the regulator. -2v 0 analog input voltage +2v led 1 - - - - 19,999 2 1 0 - 0 - 1 - 2 -19,999 - 1 - - - - -100 v +100 v > 4e1fh 4e1fh 0002h 0001h 0000h ffffh fffeh fffdh b1e0h < b1e0h adc result figure 16. max1366 transfer function?2v range -200mv 0 analog input voltage +200mv led 1 - - - - 19,999 2 1 0 - 0 - 1 - 2 -19,999 - 1 - - - - -10 v +10 v > 4e1fh 4e1fh 0002h 0001h 0000h ffffh fffeh fffdh b1e0h < b1e0h adc result figure 17. max1366 transfer function?200mv range -2v 0 analog input voltage +2v led 1 - - - 1999 2 1 0 - 0 - 1 - 2 -1999 - 1 - - - -1mv +1mv > 7cfh 7cfh 002h 001h 000h fffh ffeh ffdh 830h < 830h adc result figure 19. max1368 transfer function?2v range -200mv 0 analog input voltage +200mv led 1 - - - 1999 2 1 0 - 0 - 1 - 2 -1999 - 1 - - - -100 v +100 v > 7cfh 7cfh 002h 001h 000h fffh ffeh ffdh 830h < 830h adc result figure 18. max1368 transfer function?200mv range
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 21 leading-zero suppression the max1366/max1368 include a leading-zero sup- pression circuitry to turn off unnecessary zeros. for example, when dpset1 and dpset2 = [0,0], 0.0 is dis- played instead of 000.0 (max1366). this feature saves a substantial amount of power by not lighting unneces- sary leds. interdigit blanking the max1366/max1368 also include interdigit-blanking circuitry. without this feature, it is possible to see a faint digit next to a digit that is completely on. the interdigit-blanking circuitry prevents ghosting over into the next digit for a short period of time. the typical interdigit blanking time is 4?. - fs + fs adc output code 0 dac output voltage (v) 0 1.25 unipolar: biplolar: fs = full scale figure 20. dac output voltage vs. adc output code unipolar: biplolar: adc output code 4-20out (ma) 20 fs = full scale 0 4 - fs + fs 0 current offset enabled (en_i = 1) 12 figure 21. output current (4-20out) vs. adc output code (current offset enabled) offset enabled: offset disabled: v/i converter input ( v ) 0 4-20out (ma) 20 0 16 4 1. 25 figure 23. 4-20out output current vs. v/i converter input voltage unipolar: biplolar: adc output code 4-20out (ma) 16 fs = full scale 0 - fs + fs 0 current offset disabled (en_i = 0) 8 figure 22. output current (4-20out) vs. adc output code (current offset disabled)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 22 ______________________________________________________________________________________ applications information power-on reset at power-on, the serial interface, logic, led drivers, digital filter, modulator, and dac circuits reset. the registers return to their default values. serial interface the spi/qspi/microwire serial interface consists of a chip select ( cs ), a serial clock (sclk), a data in (din), a data out (dout), dac chip select ( cs_dac ), and an eoc output. cs and cs_dac enable access to regis- ters in the max1366/max1368. cs allows a read and write to all registers of the max1366/max1368 exclud- ing the dac register and cs_dac enables a write to the dac register (see table 8 ). eoc provides an end- of-conversion signal with a period of 200ms (f clk = 4.9152mhz). the max1366/max1368 update the adc register when eoc goes high. data is valid in the adc register when eoc returns low. the serial interface pro- vides access to 13 on-chip registers, allowing control to all the power modes and functional blocks. table 6 lists the address and read/write accessibility of all the regis- ters excluding the dac register. a logic-high on cs and cs_dac tri-states dout and causes the max1366/max1368 to ignore any signals on sclk and din. to clock data in or out of the internal shift register, drive cs or cs_dac low. sclk synchro- nizes the data transfer. the rising edge of sclk clocks din into the shift register, and the falling edge of sclk clocks dout out of the shift register. din and dout are transferred msb first (data is left justified). figures 6?0 show the detailed serial-interface timing diagrams for the 8- and 16-bit read/write operations. all communication with the max1366/max1368, with exception of the dac register, begins with a command byte on din, where the first logic one on din is recog- nized as the start bit (msb) for the command byte. the following seven clock cycles load the command into a shift register. these 7 bits specify which of the registers are accessed next, and whether a read or write operation takes place. transitions on the serial clock after the command byte transfer, cause a write or read from the device until the correct number of bits have been transferred (8 or 16). once this has occurred, the max1366/max1368 wait for the next command byte. cs must not go high between data transfers. if cs is toggled before the end of a write or read operation, the device mode may be unknown. clock in 32 zeros to clear the device state and reset the interface so it is ready to receive a new command byte. to write to the dac register, pull cs_dac low and clock in 16 data bits. data bits are clocked in msb first (see the dac operation section). on-chip registers (excluding dac register) the max1366/max1368 contain 12 on-chip registers. these registers configure the various functions of the device and allow independent reading of the adc results and writing to the led display. table 6 lists the address and size of each register. the first of these registers is the status register. the 8-bit status register contains the status flags for the adc. the second reg- ister is the 16-bit control register. this register sets the led display controls, range modes, power-down modes, offset calibration, and the reset register func- tion (clr). the third register is the 16-bit overrange register, which sets the overrange limit of the analog input. the fourth register is the 16-bit underrange regis- ter, which sets the underrange limit of the analog input. registers 5 through 7 contain the display data for the individual segments of the led. the eighth register contains the custom offset value. the ninth register contains the 16 msbs of the adc conversion result. the 10th register contains the led data. the 11th reg- ister contains the peak analog input value. the last reg- ister contains the lower 4 lsbs of the 20-bit adc conversion result.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 23 r iset (k ? )i seg ( ma) 25 20 50 10 100 5 500 1 > 2500 led driver disabled table 7. segment-current selection description cs cs_dac reserved. 0 0 read or write to on-chip registers excluding the dac register. 01 write to the dac register only. 1 0 dout is high impedance. din and sclk are ignored. 11 table 8. cs and cs_dac table fet type n-channel depletion mode i ds 30ma bv ds (v ext * - reg_vdd) min v pinchoff reg_vdd max power dissipation 30ma x (v ext - reg_vdd) min table 9. fet characteristics * v ext is the 7v to 30v loop voltage. register address rs[4:0] name width access 1 00000 status register 8 read only 2 00001 control register 16 r/ w 3 00010 overrange register 16 r/ w 4 00011 underrange register 16 r/ w 5 00100 led segment-display register 1 16 r/ w 6 00101 led segment-display register 2 16 r/ w 7 00110 led segment-display register 3 8 r/ w 8 00111 adc custom offset register 16 r/ w 9 01000 adc result register (16 msbs) 16 r/ w 10 01001 led data register 16 r/ w 11 01010 peak register 16 r/ w 12 10100 adc result register 2 (4 lsbs) 8 r/ w all other addresses reserved table 6. register-address table
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 24 ______________________________________________________________________________________ msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 start(1) r/ w rs4 rs3 rs2 rs1 rs0 x control and status registers command byte (write only) msb lsb sign over under low_batt drdy 0 0 0 status register (read only) start: start bit. the first 1 clocked into the max1366/ max1368 is the first bit of the command byte. (r/ w ): read/ write . set this bit to 1 to read from the specified register. set this bit to zero to write to the selected register. note that certain registers are read only. write commands to a read-only register are ignored. (rs4?s0): register address bits. rs4 to rs0 specify which register is accessed. x: don? care. default values: 00h this register contains the status of the conversion results. sign: latched negative-polarity indicator. latches high when the result is negative. clears by reading the sta- tus register, unless the condition remains true. over: overrange bit. latches high if an overrange condition occurs (the adc result is larger than the value in the overrange register). clears by reading the status register, unless the condition remains true. under: underrange bit. latches high if an underrange condition occurs (the adc result is less than the value in the underrange register). clears by reading the status register, unless the condition remains true. low_batt: low-battery bit. latches high if the volt- age at the lowbatt is lower than 2.048v (typ). clears by reading the status register, unless the condition remains true. drdy: data-ready bit. latches high to indicate a com- pleted conversion result with valid data. read the adc result register to clear this bit. msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 spi/ adc extclk intref dpon dpset2 dpset1 pd_dig pd_ana lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hold peak range clr seg_sel offset_cal1 offset_ cal2 enable control register (read/write) default values: 0000h this register is the primary control register for the max1366/max1368. it is a 16-bit read/write register. it is used to indicate the desired clock and reference source. it sets the led display controls, range modes, power-down modes, offset calibration, and the reset register function (clr). enable: (default = 1.) led driver enable bit. when set to 1, the max1366/max1368 enables the led display drivers. a 0 in this location disables the led dis- play drivers. offset_cal2: (default = 0.) enhanced offset-calibra- tion start bit (range = 1). to achieve the lowest possi- ble offset in the 200mv input range, perform an enhanced offset calibration by setting this bit to 1. the calibration takes about nine cycles (1800ms). after the calibration completes, set this bit to zero to resume adc conversions.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 25 msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 overrange register (read/write) offset_cal1 : (default = 0.) automatic offset-calibra- tion enable bit. when set to 1, the max1366/ max1368 disable automatic offset calibration. when this bit is set to zero, automatic offset calibration is enabled. seg_sel: (default = 0.) seg_sel segment selection bit. when set to 1, the led segment drivers use the led segment registers to display individual segments that can form letters or numbers or other information on the display. the led data register is not displayed. send the data first to the led segment-display regis- ters and then set this bit high. clr: (default = 0.) clear all registers bit. when set to 1, all registers reset to their power-on reset states after cs makes a low-to-high transition. range: (default = 0.) input range select bit. when set to zero, the input voltage range is ?v. when set to 1, the input voltage range is ?00mv. peak: (default = 0.) peak bit. when set to 1 (and the hold bit is set to zero), the led shows the result stored in the peak register (see table 6). hold: (default = 0.) hold bit. when set to 1, the led register does not update from the adc conversion results and holds the last result on the led. the max1366/max1368 continue to perform conversions during hold (table 1). pd_ana: (default = 0.) power-down analog select bit. when set to 1, the analog circuits (analog modulator and adc input buffers) go into the power-down mode. when set to zero, the device is in full power-up mode. pd_dig: (default = 0.) power-down digital select bit. when set to 1, the digital circuits (digital filter and led drivers) go into power-down mode. this also resets the values of the internal sram in the digital filter to zeros. when set to zero, the device returns to full power-up mode. when powering down pd_dig, power down the led segment drivers by clearing the enable bit to zero. dpset[2:1]: (default = 00.) decimal-point selection bits (table 2 and 3). dpon: (default = 0.) decimal-point enable bit (tables 2 and 3). intref: (default = 0.) reference select bit. for internal reference operation, set intref to 1. for external refer- ence operation, set intref to zero. extclk: (default = 0.) external clock select bit. the extclk bit controls selection of the internal clock or an external clock source. a 1 in this location selects the signal at the clk input as the clock source. a zero in this location selects and powers up the internal clock oscillator. spi/ adc : (default = 0.) display select bit. the spi/ adc bit controls selection of the data fed into led data reg- ister. a 1 in this location selects spi/qspi/microwire data (user writes this data to the led data register). a zero in this location selects the adc result register data, unless hold or peak functions are active (table 1). note: when changing any one of the following control bits: offset_cal1, range, pd_ana, pd_dig, intref, and extclk, wait 800ms before reading the adc results. default values: 7cf0h (for 3.5-digit, +1999) 4e1fh (for 4.5-digit, +19,999) the overrange register is a 16-bit read/write register (d15 is the msb). when the conversion result exceeds the value in the overrange register, the over bit in the status register latches to 1. the led shows a 1 followed by four dashes for the max1366 or a 1 followed by three dash- es for the max1368 (table 4). the data is represented in two?-complement format.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 26 ______________________________________________________________________________________ msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 underrange register (read/write) default values: 8300h (for 3.5-digit, -2000) b1e0h (for 4.5-digit, -20,000) the underrange data register is 16-bit read/write regis- ter (d15 is the msb). when the conversion result falls below the value in the underrange register, the undr bit in the status register sets to 1. the led shows a -1 followed by four dashes for the max1366 or a -1 fol- lowed by three dashes for the max1368 (table 4). the data is represented in two?-complement format. default values: 0000h msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 a1 g1 d1 f1 e1 dp2 x b0 lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c0 a0 g0 d0 f0 e0 dp1 0 led segment-display register 1 (read/write) led segment-display register 1 is a 16-bit read/write register. when the led bit (in the control register) is set to 1, the max1366/max1368 provide direct access to individual led segments. the bits in the led segment- display register determine if a segment is on or off. write a zero to turn on a segment and a 1 to turn off a segment. dp1: segment dp driver bit of digit 1. the default value turns on the led segment. e0: segment e driver bit of digit 0. the default value turns on the led segment. f0: segment f driver bit of digit 0. the default value turns on the led segment. d0: segment d driver bit of digit 0. the default value turns on the led segment. g0: segment g driver bit of digit 0. the default value turns on the led segment. a0: segment a driver bit of digit 0. the default value turns on the led segment. c0: segment c driver bit of digit 0. the default value turns on the led segment. b0: segment b driver bit of digit 0. the default value turns on the led segment. x: don? care. dp2: segment dp driver bit of digit 2. the default value turns on the led segment. e1: segment e driver bit of digit 1. the default value turns on the led segment. f1: segment f driver bit of digit 1. the default value turns on the led segment. d1: segment d driver bit of digit 1. the default value turns on the led segment. g1: segment g driver bit of digit 1. the default value turns on the led segment. a1: segment a driver bit of digit 1. the default value turns on the led segment.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 27 msb bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 f3 e3 dp4 minus b2 c2 a2 g2 lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d2 f2 e2 dp3 x b1 c1 0 led segment-display register 2 (read/write) default values: 0000h led segment-display register 2 is a 16-bit read/write register. when the seg_sel bit (in the control register) is set to 1, the max1366/max1368 provide direct access to individual led segments. the bits in the led segment-display register determine if a segment is on or off. write a zero to turn on a segment and a 1 to turn off a segment. c1: segment c driver bit of digit 1. the default value turns on the led segment. b1: segment b driver bit of digit 1. the default value turns on the led segment. minus: segment minus driver bit. the default value turns on the led minus segment. setting this bit to 1 enables the plus sign on the led display. dp3: segment dp driver bit of digit 3. the default value turns on the led segment. e2: segment e driver bit of digit 2. the default value turns on the led segment. f2: segment f driver bit of digit 2. the default value turns on the led segment. d2: segment d driver bit of digit 2. the default value turns on the led segment. g2: segment g driver bit of digit 2. the default value turns on the led segment. a2: segment a driver bit of digit 2. the default value turns on the led segment. c2: segment c driver bit of digit 2. the default value turns on the led segment. b2: segment b driver bit of digit 2. the default value turns on the led segment. dp4: segment dp driver bit of digit 4. the default value turns on the led segment (max1366 only). e3: segment e driver bit of digit 3. the default value turns on the led segment (max1366 only). f3: segment f driver bit of digit 3. the default value turns on the led segment (max1366 only). default values: 00h led segment-display register 3 is an 8-bit read/write register. when the seg_sel bit (in the control register) is set to 1, the max1366/max1368 provide direct access to individual led segments. the bits in the led segment-display register determine if a segment is on or off. write a zero to turn on a segment and a 1 to turn off a segment. d3: segment d driver bit of digit 3. the default value turns on the led segment (max1366 only). g3: segment g driver bit of digit 3. the default value turns on the led segment (max1366 only). a3: segment a driver bit of digit 3. the default value turns on the led segment (max1366 only). c3: segment c driver bit of digit 3. the default value turns on the led segment (max1366 only). b3: segment b driver bit of digit 3. the default value turns on the led segment (max1366 only). bc _ : segment b and c driver bit of digit 3 (3.5 digits) or digit 4 (4.5 digits). the default value turns on the led segment. x: don? care. msb lsb xx bc_ b3 c3 a3 g3 d3 led segment-display register 3 (read/write)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 28 ______________________________________________________________________________________ default values: 0000h in addition to automatic offset calibration, the max1366/max1368 offer a user-defined custom offset 16-bit read/write register. the final result of the adc conversion is the input after autocalibration minus the value in the custom offset. the custom offset value is stored in this register. d15 is the msb. the data is represented in two?-complement format. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 adc custom offset-calibration register 3 (read/write) default values: 0000h adc result register 1 is a 16-bit read-only register. this register stores the 16 msbs of the adc result. the data is represented in two?-complement format. for the max1366, the data is 16-bit and d15 is the msb. for the max1368, the data is 12-bit, d15 is the msb, and d4 is the lsb. msb lsb (max1368) lsb (max1366) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 adc result register 1 (read only) default values: 00h adc result register 2 is an 8-bit read-only register. this register stores the 4 lsbs of the adc result. use this result with the result in adc result register 1 to form a 20-bit two?-complement conversion result. msb lsb d3 d2 d1 d0 0 0 0 0 adc result register 2 (read only) default values: 0000h the led data register is a 16-bit read/write register. this register updates from adc result register 1 or from the serial interface by selecting the spi/adc bit in the control register. the data is represented in two?-com- plement format. for the max1366, the data is 16-bit and d15 is the msb. for the max1368, the data is 12-bit, d15 is the msb, and d4 is the lsb, followed by 4 trailing sub-bits. msb lsb (max1368) lsb (max1366) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 led data register (read/write)
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 29 default values: b1e0h the peak data register is a 16-bit read-only register. set the peak bit to 1 to enable the peak function. this register stores the peak value of the adc conversion result. first, the current adc result is saved to the peak register, then the new adc conversion result is compared to this value. if the new value is larger than the value in the peak register, the max1366/max1368 save the new value to the peak register. if the new value is less than the value in the peak register, the value in the peak register remains unchanged. set the peak bit to zero to clear the value in the peak register. the data is represented in two?-complement format. for the max1366, the data is 16-bit and d15 is the msb. for the max1368, the data is 12-bit, d15 is the msb, and d4 is the lsb followed by 4 trailing sub-bits. msb lsb (max1368) lsb (max1366) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 led data register (read/write) dac operation for the max1366/max1368, a voltage proportional to the adc input is available at dacvout. connect dacvout to conv_in for normal operation. (see figure 20 for dac transfer function). in normal operation, pull dacdata_sel low to use the adc output as the dac input. pull dacdata_sel high to allow data to be written to the dac register using the spi/qspi/microwire interface. once dacdata_sel is pulled high, the three digital inputs ( cs_dac , din, and sclk) load the digital input data serially into the dac. (see figure 11 .) to clock data into the dac shift register, drive cs_dac low. sclk synchronizes the data transfer. immediately, following cs_dac high-to-low transition, the data shifts synchronously into the serial shift register on the rising edge of the serial clock input (sclk). after 16 data bits have been loaded into the serial input register, the data latches to the dac register on the rising edge of cs_dac . the dac output updates on the next conver- sion clock (2.5hz). din is transferred msb first. reference adc reference the max1366/max1368 reference sets the full-scale range of the adc transfer function. with a nominal 2.048v reference, the adc full-scale range is ?v with range = gnd. with range = dv dd, the full-scale range is ?00mv. a decreased reference voltage decreases full-scale range (see the transfer functions section). the max1366/max1368 accept either an external ref- erence or an internal reference (intref). the intref logic selects the reference mode (see the control register (read/write) section). the default power-on state sets the max1366/max1368 to use the external reference with the intref bit cleared to zero. for internal-reference operation, set the intref bit to one , connect ref- to gnd, and bypass ref+ to gnd with a 4.7? capacitor. the internal reference provides a nominal 2.048v source between ref+ and gnd. the internal-reference temperature coefficient is typically 40ppm/?. for external-reference operation, set intref to gnd. ref+ and ref- are fully differential. for a valid external- reference input, v ref+ must be greater than v ref- . bypass ref+ and ref- with a 0.1? or greater capaci- tor to gnd in external-reference mode. figure 14 shows the max1366/max1368 operating with an external single-ended differential reference. in this figure, ref- is connected to the top of the strain gauge and ref+ is connected to the midpoint of the resistor-divider of the supply. figure 15 shows the max1366/max1368 operating with an external single-ended reference. in this figure, ref- is connected to gnd and ref+ is driven with an exter- nal 2.048v reference. bypass ref+ to gnd with a 0.1? capacitor. dac reference the dac of the max1366/max1368 accepts either an external reference or an internal reference. for external- reference operation, disable the dac reference buffer by setting refsele to dv dd and connect a voltage source to ref_dac. for internal-reference operation, enable the dac refer- ence buffer by setting refsele to gnd. in this mode, leave refdac floating.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 30 ______________________________________________________________________________________ in either internal or external reference operation, bypass ref_dac with a 0.1? capacitor to gnd. choose a reference with output impedance (load regu- lation equivalent) of 100m ? or less, such as the max6126. for best performance, use an external source from the adc and dac. offset calibration the max1366/max1368 offer on-chip offset calibration. the device offset calibrates during every conversion when the offset_cal1 bit is zero in the control regis- ter. enhanced offset calibration is only needed in the max1366 when the range bit = 1. it is performed on demand by setting the offset_cal2 bit to 1. enhanced offset calibration enhanced offset calibration is a more accurate calibra- tion method that is needed in the case of the ?00mv range and 4.5-digit resolution. the max1366 performs enhanced calibration on demand by setting the offset_cal2 bit to 1. power-down modes the max1366/max1368 feature independent power-down control of the analog and digital led driver? circuitry. writing a 1 to the pd_dig and pd_ana bits in the con- trol word, powers down the analog and digital circuitry, reducing the supply current to 268? (typ). pd_dig powers down the digital filter, while pd_ana powers down the analog modulator and adc input buffers. writing a zero to the enable bit in the control word powers down the led drivers. peak the max1366/max1368 feature peak-detection circuitry. when activated (peak bit = 1), the devices display only the highest voltage measured to the led. hold the max1366/max1368 feature data-hold circuitry. when activated (hold bit = 1), the device holds the current reading on the led. low battery the max1366/max1368 feature a low-battery detection input. when the voltage at lowbatt drops below 2.048v (typ), lowbatt in the status register goes high. strain-gauge measurement connect the differential inputs of the max1366/ max1368 to the bridge network of the strain gauge. in figure 14 , the analog supply voltage powers the bridge network and the max1366/max1368, along with the reference voltage. the max1366/max1368 handle an analog input voltage range of ?00mv and ?v full scale. the analog/reference inputs of the parts allow the analog input range to have an absolute value of anywhere between -2.2v and +2.2v. thermocouple measurement figure 15 shows a connection from a thermocouple to the max1366/max1368. in this application, the max1366/max1368 take advantage of the on-chip input buffers that allow large source impedances on the front end. the decoupling capacitors reduce noise pickup from the thermocouple leads. to place the differential voltage from the thermocouple at a suitable common- mode voltage, the ain- input of the max1366/max1368 is biased to gnd. use an external temperature sensor, such as the ds75, and a microcontroller to perform cold- junction temperature compensation. transfer functions adc transfer functions figures 16?9 show the transfer functions of the max1366/max1368. the output data is stored in the adc data register in two? complement. the transfer function for the max1366 with ain+ - ain- 0 and range = gnd is: the transfer function for the max1366 with ain+ - ain- < 0 and range = gnd is: the transfer function for the max1368 with ain+ - ain- 0 and range = gnd is: the transfer function for the max1368 with ain+ - ain- < 0 and range = gnd is: the transfer function for the max1366 with ain+ - ain- 0 and range = dv dd is: () . , 51 024 20 000 10 count vv vv xx ain ain ref ref = ? ? ? ? ? ? + ? ? + ? ? () . 41 024 2000 1 count vv vv x ain ain ref ref = ? ? ? ? ? ? + + ? ? + ? ? () . 31 024 2000 count vv vv x ain ain ref ref = ? ? ? ? ? ? + ? ? + ? ? () . , 21 024 20 000 1 count vv vv x ain ain ref ref = ? ? ? ? ? ? + + ? ? + ? ? () . , 11 024 20 000 count vv vv x ain ain ref ref = ? ? ? ? ? ? + ? ? + ? ?
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 31 the transfer function for the max1366 with ain+ - ain- < 0 and range = dv dd is: the transfer function for the max1368 with ain+ - ain- 0 and range = dv dd is: the transfer function for the max1368 with ain+ - ain- < 0 and range = dv dd is: dac transfer functions figure 20 shows the dac transfer function for the max1366/max1368 in unipolar and bipolar modes. the transfer function for the dac in the max1366/ max1368 unipolar mode is: where n = two? complement adc output code. in unipolar mode, v dacvout is equal to 0v for all two? complement adc codes less than zero (see figure 21 ). the transfer function for the dac in the max1366/ max1368 in bipolar mode is: where n = two? complement adc output. writing into the dac independently a user can independently write to the dac but cannot input codes greater than +19,999 or less than -19,999. in bipolar mode, a -19,999 dac code provides 4ma (0ma) output current and a +19,999 dac code pro- vides a 20ma (16ma) output current. voltage-to-current transfer function figures 20 and 21 show the max1366/max1368 trans- fer function of the output current (4-20out) versus the adc output code. figure 23 shows the max1366/max1368 transfer func- tion of the output current (4-20out) versus the input voltage of the v/i converter. the transfer function for the max1366/max1368 with the current offset enabled (en_i is high) is: the transfer function for the max1366/max1368 with the current offset disabled (en_i is low) is: supplies, layout, and bypassing power up av dd and dv dd before applying an analog input and external-reference voltage to the device. if this is not possible, limit the current into these inputs to 50ma. when the analog and digital supplies come from the same source, isolate the digital supply from the analog supply with a low-value resistor (10 ? ) or ferrite bead. for best performance, ground the max1366/ max1368 to the analog ground plane of the circuit board. avoid running digital lines under the device as this can couple noise onto the ic. run the analog ground plane under the max1366/max1368 to mini- mize coupling of digital noise. make the power-supply lines to the max1366/max1368 as wide as possible to provide low-impedance paths and reduce the effects of glitches on the power-supply line. shield fast-switching signals, such as clocks, with digital ground to avoid radiating noise to other sections of the board. avoid running clock signals near the analog inputs. avoid crossover of digital and analog signals. running traces that are on opposite sides of the board at right angles to each other reduces feedthrough effects. a microstrip technique is best, but is not always possible with dou- ble-sided boards. with this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is important when using high-resolution adcs. decouple the supplies with 0.1? ceramic capacitors to gnd. place these components as close to the device as possible to achieve the best decoupling. selecting segment current a resistor from iset to ground sets the current for each led segment. see table 7 for more detail. use the fol- lowing formula to set the segment current: i v r x seg iset = ? ? ? ? ? ? 120 400 . iout ma xv conv in ? 16 125 . _ iout ma xv ma conv in ?+ 16 125 4 . _ v n xv dacvout ref = + 19 999 6536 , v n xv dacvout ref = ? 32 768 1 , () . 81 024 2000 10 1 count vv vv xx ain ain ref ref = ? ? ? ? ? ? + + ? ? + ? ? () . 71 024 2000 10 count vv vv xx ain ain ref ref = ? ? ? ? ? ? + ? ? + ? ? () . , 61 024 20 000 10 1 count vv vv xx ain ain ref ref = ? ? ? ? ? ? + + ? ? + ? ? note: the input at v conv_in expects a source impe- dence of typically 6k ? when driving v conv_in externally.
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 32 ______________________________________________________________________________________ r iset values below 25k ? increase the i seg . however, the internal current-limit circuit limits the i seg to less than 30ma. at higher i seg values, proper operation of the device is not guaranteed. in addition, the power dissipat- ed may exceed the package power-dissipation limit. choosing supply voltage to minimize power dissipation the max1366/max1368 drive a peak current of 25.5ma into leds with a 2.2v forward-voltage drop when operat- ed from a supply voltage of at least 3.0v. therefore, the minimum voltage drop across the internal led drivers is 0.8v (3.0v - 2.2v = 0.8v). the max1366/max1368 sink when the outputs are operating and the led segment drivers are at full current (8 x 25.5ma = 204ma). for a 3.3v supply, the max1366/max1368 dissipate 224.4mw ((3.3v - 2.2v) x 204 = 224.4mw). if a higher supply volt- age is used, the driver absorbs a higher voltage, and the driver? power dissipation increases accordingly. however, if the leds used have a higher forward-voltage drop than 2.2v, the supply voltage must be raised accordingly to ensure that the driver always has at least 0.8v headroom. for an ledv supply voltage of 2.7v, the maximum led forward voltage is 1.9v to ensure 0.8v dri- ver headroom. the voltage drop across the drivers with a nominal +5v supply (5.0v - 2.2v = 2.8v) is almost three times the drop across the drivers with a nominal 3.3v supply (3.3v - 2.2v = 1.1v). therefore, the driver? power dissipation increases three times. the power dis- sipation in the part causes the junction temperature to rise accordingly. in the high ambient temperature case, the total junction temperature may be very high (> +125?). at higher junction temperatures, the adc per- formance degrades. to ensure the dissipation limit for the max1366/max1368 is not exceeded and the adc performance is not degraded; a diode can be inserted between the power supply and ledv. selecting depletion-mode fet an external depletion-mode fet (dmos) works in con- junction with the regulator circuit to supply the v/i con- verter with loop power. reg_force regulates the gate of the dmos so that the drain voltage is 5.2v (typ) and allows the 4?0ma (0 to 16ma) loop to be directly pow- ered from a 7v to 30v supply. dmos i ds consists of the current output at 4-20out, a 4ma offset current, and 1ma (typ) consumed by the v/i converter. for offset-enabled mode (en_i = 1): i ds = i 4-20out + 4ma + 1ma for offset-disabled mode (en_i = 0): i ds = i 4-20out + 1ma where i ds is the current in the dmos. table 9 provides the fet characteristics for selecting an external dmos transistor. the dn25d fet transistor from supertex meets all the requirements of table 7. other suitable transistors include nd2020l and nd2410l from siliconix. connect a 0.1? capacitor between cmp and reg_force to ensure stable regulator compensation. definitions integral nonlinearity (inl) inl is the deviation of the values on an actual transfer function from a straight line. this straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max1366/ max1368 is measured using the end-point method. differential nonlinearity (dnl) dnl is the difference between an actual step width and the ideal value of ? lsb. a dnl error specification of less than ? lsb guarantees no missing codes and a monotonic transfer function. rollover error rollover error is defined as the absolute-value differ- ence between a near positive full-scale reading and near negative full-scale reading. rollover error is tested by applying a full-scale positive voltage, swapping ain+ and ain-, and adding the results. zero-input reading ideally, with ain+ connected to ain-, the max1366/ max1368 led displays zero. zero-input reading is the measured deviation from the ideal zero and the actual measured point. gain error gain error is the amount of deviation between the mea- sured full-scale transition point and the ideal full-scale transition point. common-mode rejection (cmr) cmr is the ability of a device to reject a signal that is common to both input terminals. the common-mode signal can be either an ac or a dc signal or a combi- nation of the two. cmr is often expressed in decibels. normal-mode 50hz and 60hz rejection (simultaneously) normal-mode rejection is a measure of how much output changes when 50hz and 60hz signals are injected into only one of the differential inputs. the max1366/ max1368 sigma-delta converter uses its internal digital filter to provide normal-mode rejection to both 50hz and 60hz power-line frequencies simultaneously.
power-supply rejection (psr)?dc psr is a measure of the data converter? level of immu- nity to power-supply fluctuations. psr assumes that the converter? linearity is unaffected by changes in the power-supply voltage. power-supply rejection ratio (psrr) is the ratio of the input signal change to the change in the converter output. psrr is typically mea- sured in db. power-supply rejection?/i converter psr is a measure of the data converter? level of immu- nity to power-supply fluctuations. psr assumes that the converter? linearity is unaffected by changes in the power-supply voltage. note that the v/i converter cur- rent output (4?0ma) power-supply rejection is with respect to the 7v to 30v loop supply. max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 33 max1366 max6126 0.1 f 10 f 0.1 f 0.1 f 10 f 0.1 f 10 f l iso r l 2.7v to 5.25v 4.75v to 5.25v depletion- mode fet v ext 7v to 30v 4?0ma plc input adc ain+ in dac_vdd supply voltage 0.1 f ain- led_en 4?0ma/0 to 16ma current-loop output ledv dv dd av dd dac_vdd gnd_dac ref_dac set negv gnd ref- ref+ gnd_v/i ledg dacvout outf outs conv_in en_bpm en_i dacdata_sel refsele clk sclk cs c dig0?ig4 digit connections sega?egdp segment connections v in cmp gnds 0.1 f 0.1 f gnd reg_force reg_vdd reg_amp 4-20out 25k ? lowbatt dv dd cs_dac eoc dout din max1366 typical operating circuit
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output 34 ______________________________________________________________________________________ max1368 max6126 0.1 f 10 f c 0.1 f 0.1 f 10 f 10 f l iso r l 2.7v to 5.25v 4.75v to 5.25v depletion- mode fet v ext 7v to 30v 4?0ma plc input adc ain+ in 0.1 f ain- led_en 4?0ma/0 to 16ma current-loop output ledv dv dd av dd dac_vdd gnd_dac digo ref_dac set negv gnd ref- ref+ gnd_v/i ledg dacvout outf outs conv_in en_bpm en_i dacdata_sel refsele dig1?ig4 digit connections sega?egdp segment connections v in cmp gnds gnd reg_force reg_vdd reg_amp 4-20out 25k ? clk sclk cs cs_dac eoc dout din dv dd lowbatt 0.1 f dac_vdd supply voltage 0.1 f 0.1 f max1368 typical operating circuit
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output ______________________________________________________________________________________ 35 segb sega dig4 dig3 dig2 dig1 dig0 ledg cs din dout sclk ain+ ain- gnd av dd dv dd set reg_vdd reg_force reg_amp cmp dac_vdd dacvout 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 ref_dac tqfp max1366 max1368 conv_in 4-200ut gdn_dac gnd_v/i en_bpm en_i refsele dacdata_sel cs_dac clk eoc 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 ref+ ref- lowbatt negv led_en segdp segg segf sege segd segc ledv top view pin configuration chip information transistor count: 83,463 process: cmos
max1366/max1368 microcontroller-interface, 4.5-/3.5-digit panel meters with 4?0ma output package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 36 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. 32l/48l,tqfp.eps e 1 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm e 2 2 21-0054 package outline, 32/48l tqfp, 7x7x1.4mm

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